pulse regenerator

IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-21, NO. 2, APRIL 1986 331 Regenerator Chip Set for High-Speed Digital Tr...

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IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-21, NO. 2, APRIL

1986

331

Regenerator Chip Set for High-Speed Digital Transmission DAVID G. ROSS, MEMBER,IEEE, STAlNL13Y F. MOYER, ROBERT

WALLACE H. ECKTON, JR., SENIORMEMBER,IEEE, M. PASKI, MEMBER,IEEE, AND DAVID G. EHRENBERG

~bstract —We have developed a custom two-chipset containing ail of the active circuitry necessaryfor regenerationof digitalelectricalsignals in

INPUT AGC

b

a 300-Mbit/s fiber-optic transmission system. The set includes an automatic gain control (KC) amplifier with gain-bandwidth plroduct in excess of 100 GHz, and a decision circuit with excellent dynamic sensitivity, measured up to 650 Mbit/s. ‘fhe chips are fabricated usirsg a 2.5-pm fully complementary bipolar process.

I.

DECISION

RETIMING

INTRODUCTION

H

BPF

f 0/2

HE EXTREMELY high transmission capacity and very low loss obtainable in single-mode optical fiber make it a highly desirable medium for undersea transoceanic transmission systems. The first such system, TAT-8, is targeted for deployment in the Atlantic in 1988 [1]. The electronics for the electro-optical undersea regenerators must exhibit a combination of high performance and high reliability. One key element in the design of reliable regenerators is reduction of part count, through integration of the electronics, Another is reduction of current drain, through use of efficient circuit designs. 1111 this paper we describe the monolithic circuitry used for the regeneration of high-speed electrical signals within the optical regenerator. Other aspects of the regenerator design are covered’ elsewhere [2],[3]. The topics we discuss include: a brief overview of the application, showing how the chips are used; the integrated circuit technology, and characteristics of the transistors; the chip architectures; lnovel circuit features; and performance of the integrated circuits and of the complete regenerator.

OUTPUT REGENERATED OATA

BPF fB

T

300

MB/s

REGENERATOR

Fig. 1. Block diagram of the digitaf regenerator, showing the three major active functional blocks and the associated bandpass filters.

be brought to a uniform level to provide maximum uniformity in the reconstructed pulses. We accomplish tlhis using a broad-band linear amplifier with automatic gain control (AGC); the amplifier samples its own output, detects the average level, and adjusts its gain accordingly. The AGC amplifier produces two equal in-phase outputs. One of the AGC outputs is used to derive a local clock —in our case, at 295.6 MHz—from the data stream by a “combination of linear filtering and nonlinear processing. This takes place in the retiming circuit. The second AGC output, and the local clock, are then used by the decision circuit to reconstruct the bits with precise amplitude and transition spacing. We have partitioned our regenerator so that the AGC, retiming, and decision circuits each use a single monolithic integrated circuit. Moreover, we have constructed one of II. THE DIGITAL REGENERATOR the chips so that it may be used in either the AGC or retiming application. Thus the complete electrical regeneraThe purpose of the regenerator is to reshape and retime tor is formed from a two-chip set. the electrical pulses in a binary data stream. A block A more complete discussion of the overall regenerator is diagram of the regenerator is shown in Fig. 1. The process provided in [2]. of regeneration is described below. The input pulses, which may vary in amplitude over a wide range— about 3 to 300 mV in our application—must

III.

INTEGRATED-CIRCUIT TECHNOLOGY

The chip set makes use of a process Manuscript received July 5, 1984; revised July 12, 1985. D, G, Ross, R. M. Paskr, and D. G. Ehrenbcrg are with AT&T Bell Laboratories, Holmdel, NJ 07733. S. F. Moyer and W. H. Eckton are with AT&T Bell Laboratories, Reading, PA 196040 IEEE Log Number 84072f/5.

0018-9200/86/0400-0331

technology

called

Microwave Complementary Bipolar Integrated Circuits (MCBIC). This is an extension of AT&T’s CBIC technology, which has been reported in this journal at other times [4],[5]. Like CBIC, MCBIC produces fully comple$01.00 01986 IEEE

332

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 2, APRIL 1986 Parameter

FREQUENCYRESPONSE(fT)COMPARISON

NPN —

IC

vCE —.

PNP — . 15flm

.25um

Base Width fT

3mA

3V

4 GHz

2.5

80-130

50-70

15V

12V

GHz

I

I

3vlmA

P vCE

lmA

(S US)

yJ~

VBE

Fig. 4.

~

~

Summary of typical device characteristics.

vARIABLE-GAIN

FIxED-GAIN

STAGES

STAGE

I

VCE=3V

.3

Fig. 2.

I

I

,5

1

I

I

I

I

235 Ic (mA)

10

I 20

I

Collector current versus base-emitter voltage plot for typical n-p-n and p-n-p transistors; match is within 10 mV.

COLLECTORCURRENTVS BASE-EMITTER VOLTAGE

I CONTROL

&M PLITuDE

AMP

b MONITOR

FREQuENCY

OUTPUT

10-2

I

I

AGC



~o_4

_

DOUBLER

RETIMING

I

I

I

VCE=3V 10-3

DETECTOR-AK

Fig. 5.

/RETIMING

CHIP

Block diagram of the AGC/retiming chip.

~ > 510–5



“ 10-6

PNP 10-7

-

/? 10-8 .4

Fig.

3,

~

i~(

I

.5

.6

I .1 .8 VBE(VOLTS)

.9

1.0

versus IC for typical n-p-n and p-n-p devices.

mentary n-p-n and p-n-p transistors, and it uses junction isolatio-n. Ii differs from- standard CBIC in that the minimum feature size is 2.5 pm, and the transistor f~ is over 2.5 GHz. Each of these is about a factor of 7 different—the features smaller and ~~ higher-from the standard CBIC devices. In that sense, the MCBIC technology may be thought of as a merger of CBIC with the single-conductivity Microwave Junction Isolated Monolithic (MJIM) process [6]. Fig.2 shows the extent to which the n-p-n and p-n-p

devices are matched in their dc characteristics; the IC versus V~, curves are typically within a few millivolts over several orders of magnitude in current. The plot of ~* versus IC in Fig. 3 shows that the devices are also rather well matched in their high-frequency characteristics. The ~~’s of the two device types peak at about the same current, and the ~~ of each device is within 80 percent of its peak value over the range from 1 to 9 mA. These characteristics allow us to design complementary circuitry for use from dc to hundreds of megahertz. A summary of typical transistor characteristics is provided in Fig. 4.

1

1

I

6 GAIN

Fig. 6.

CELL

Schematic of the complementary-symmetry wide-band gain cell used in the ACE retiming amplifier.

A. A CG/Retiming

Chip

The chip used for the AGC and retiming applications comprises four functional blocks as shown in Fig. 5. These are: a wide-band variable-gain section with two gain stages, a wide-band fixed-gain section, also having two gain stages; a nonlinear section that serves as either an amplitude detector for the AGC function, or as a frequency doubler for retiming; and a low-frequency amplifier for AGC. One of the chip’s features, made possible by the MCBIC technology, is the wide-band gain cell, shown in Fig. 6. The cell is actually a complementary-symmetry push–pull pair of amplifiers, each one of which is shown within an inner rectangle in the figure. Push–pull operation maximizes the available gain and the achievable output level for a given

333

ROSS d al.: REGENERATORCHIP FOR DIGITAL TRANSMISSION

FIxED

GAIN 8008-

vARIABLE

GAIN 43d8-

IN o–

0– 108

250’MHz

k

NO FEED8ACK

SERIES SHUNT FEEDBACK

75 fl

75 fi

G kW

TERMINATION ❑

108 GM?

(a)

Am

TERMIN&TIO!. CONNECTED

(b) AMPLIFIER CHIP GAIN VS FREOUENCY

r

It,

,LPF, CHIP CONNECTIONS

I Q)

Fig. 8. Measured gain versus fre uency plots for the amplifier chip: (a) with no feedback, outputs gange$ and (b) with feedback, as used in the AGC application.

FOR AGC

(a)

OUT

sultant split in the output current halves the available gain and level at each output; however, since the outputs are in phase, the two outputs may be wired together to restore the single-output performance. The two outputs are used individually in the AGC application, and ganged in the retiming application, as shown in Fig. 7. The two applications are discussed in more detail below. B. A GC Connections

L---I BPF

CHIP

CONNECTIONS

FOR RETIMING

(b) Fig. 7.

The chip connections for the AGC application are shown in Fig. 7(a). Series and shunt feedback networks are added for gain shaping and impedance matching in the fixed-gain cells. The data stream enters at the input to the variable-gain section, and exists from one of the two outputs of the fixed-gain section. One of the outputs is sampled by the amplitude detector, from which the output is filtered and compared against a reference, the difference being used to drive the control amplifier, completing the AGC loop.

Chip connections for: (a) AGC and (b) retiming applications.

C. Retiming Connections bias current. This is quite important in our application, for a variety of reasons, which are discussed in [2]. IEachhalf of the pair is a folded cascode with an emitter-follower input buffer; this configuration maximizes the cell’s open-loop bandwidth. The gain cell is a three-terminal device. The terminals are labeled B, E, and C because they correspond to the base, emitter, and collector of a bipolar transistor. The cell may in fact be thought of as a bipolar transistor which provides its own bias, and whose base, emitter, and collector are all at the same potential. In the figure, the terminals are all referenced to ground. as they are in our application. As with the transistor, we may add shunt feedback from the “base” to the “collector” terminals, or series feedback from the “emitter” to ground (the dashed lines in the drawing) when the device is used in the “common emitter” connection—as we use it. If desired, the cell could be used in any of the standard transistor configurations. Unlike the transistor, however, no consideration need be given to dc blocking, since the terminals lie on an equipotential. This allows us to use any feedback network, on or off chip as desired. As the drawing shows, an additional in-phase output has been added by doubling the output transistors. The re-

Connections for the retiming application are provided in Fig. 7(b). The data stream, which has been filtered symmetrically about the half-baud frequency— 147.8 MHz in our case— is applied to the nonlinear device, which produces at its output a signal having uniformly spaced zero crossings at the baud frequency [7]. This is then filtered using a narrow-band (surface acoustic wave) filter [8] at the baud frequency, and amplified by the entire wide-band chain, which uses series and shunt feedback to control gain and impedance levels. D. Chip Performance The performance of the wide-band amplifier chain is shown in Fig. 8. The open-loop gain is typically 60 dB, and the 3-dB bandwidth is over 100 MHz; the gain-bandwidth product is thus over 100 GHz, with the outputs ganged. In the AGC connection, with feedback applied and the outputs separated, gain to each output is typically 43 dB, and the bandwidth is over 200 MHz. In the retiming application, with the outputs ganged and feedback applied, gain is typically over 40 dB at 300 MHz. The nonlinear device is a simple even-order function; its measured characteristic is shown in Fig. 9. The characteris-

334

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 2, APRIL 1986

— WXISIW



ciWldT oa.AY FLP.FW

CO)WARATOR

CLOCK

L—



Fig. 11. I NkJT

Fig. 9.

Block diagram of the decision-circuit chip.

-—

— .— lAICH

I

MEASURED CHARACTER ISTIC AMPLITuDE DETECTOR / FREQUENCY OOUBLER

——



Q

I

Measured input/output characteristics of the nonlinear block in the AGC/retimmg chip. DATA

20

our

1

--1--------Fig. 12.

.10

I

-10

I 10

0

INPUT

MEASURED

Fig 10.

AGC

Measured input/output

tic has minimum

transfer

1

I

20

30

AGC

loop.

level characteristic of the closed AGC loop.

gain close to the origin,

for

T

‘$s A

Schematic of the latch circuitry in the decision circuit

40

CHARACTERISTIC

Large-signal constant



dO

to avoid

second-harmonic

output

is

above 200-mV peak to peak, where it is used in the retiming application. The measured control characteristic of the complete AGC loop is shown in Fig. 10. Output level is held within 1 dB over a 40-dB range in input. approximately

IN

I

detection of circuit noise; the gain is maximum for signals in the vicinity of 100-mV peak to peak. where h is used in the

OATA

input

signals

E. Decision Circuit For descriptive purposes, the decision circuit may be divided into three sections (in fact, there is a fourth section, not involved in the regeneration process, which will not be considered here–see [2]). A block diagram is provided in Fig. 11. The “data” circuitry receives the data stream from the AGC amplifier and quantizes it into uniform one and zero levels; it then resets the pulse transitions in response to the local clock, using two clocked latches, and delivers the reconstructed pulses to the output line through a buffer. The “clock” circuitry receives the local clock from the retiming circuit, quantizes it, and distributes it to the latches. The local clock is also distributed to the third section of the chip, the “failsafe” circuitry. The failsafe mechanism consists of: a multiplier, which multiplies the

clock by its own complement; an integrator, which develops a voltage proportional to the input clock level; and a comparator. Together, they form a threshold-type amplitude detector. Should the input clock level drop too low, the comparator output will disable the latches, enabling the quantized data to pass through the output. Without this feature, loss of clock would cause the data to be blocked, causing failure of the transmission link. The latch topology shown in Fig. 12 is typical of the circuitry used throughout. The complementary structure achieves very high internal gain, while also allowing the input and output connections to be at the same potential, for cascadability. The latching mechanism maybe enabled or defeated by a control current. This is the mechanism controlling the failsafe operation. Variants on this basic complementary differential structure make up much of the remaining circuitry on both the decision and amplifier chips; it has been transfigured into a quantizer, a multiplier, and the amplitude detector/frequency doubler. The high gain of the logic circuitry enables this decision circuit to demonstrate an extremely low ambiguity level. Only 2-mV peak-to-peak input is needed to produce an error-free output at 300 Mbit/s. Only 20 mV is needed at 650 Mbit/s. The penalty for removing the local clock at 300 Mbit/s is a barely visible amount of additional jitter on the pulse transitions, as shown in Fig. 13. A plot of bit-error rate versus signal-to-noise ratio shows that the decision process varies by only about 0.1 dB from the theoretical ideal. This is the most nearly ideal performance of any circuit we have measured.

ROSS et d:

335

REGENERATOR CHIP FOR DIGITAL TRANSMISSION

operational amplifier using complementary PNP’s,” IEEE J. SolidStafe Circuits, Dec. 1974.

2

mv

[5] R.R. Cordell and W.G. Garrett, “A highly stable VCO for application in monolithic phase-locked loops,” IEEE J. Solid-State Circuits, Dec. 1975. [6] W. Kruppa and F.D. Wafdhauer, “A UHF monolithic operationdf ~Plifier,” IEEE Int. Solid-state circuitsCon~.,Feb. 1978. [7] L.E. Franks and J.P. Bubrowske, “Statistical properties of timing jitter in a PAM timing recovesy scheme,” IEEE Trans. Comrnun., July 1974. [8] R.L. Rosenberg? D.G. Rcks, P.R. Trischitta~ D.A. Fishman, and C.B. Armitage, “ Optlcaf fiber repeatered transmission systems using SAW filters,” IEEE Trans. Sonics Untrason., May 1983.

p-p

(c

120

m

w’

ERROR-FREEOUTPUTSFROM OECISIONCHIP WITH VARIOUS INPUTS

Fig. 13. Oscilloscope photographs of error-free outputs from the decision, circuits: (a) with 2-mV p-p input at 300 Mbit/s; (b) with 20-mV p-p input at 650 MbIt/s; and (c) with and without clock at 300 Mbit/s,

IV.

REGENERATORPERFORMANCE

The electrical regenerator formed from this chip set meets or exceeds all of our performance goals at 300 Mbit/s. Laboratory tests on prototype circuits show that it regenerates signals at 10-9 or better error rate with input levels as small as 2-mV peak to peak or as high as 2 V. It produces a regenerated signal of 375-mV peak to peak into 75 G?.The regeneration electronics consume 150 mA from + 5-V sources. Data on performance of the complete optical regenerator in an undersea repeater are provided in [2]. V. We active

have

developed

circuitry

necessary

David G. Ross (M74) received the B.S.E.E. and M.S.E.E. degrees from the University of Michigan, Arm Arbor, in 1970 and 1971, respectively. In 1971, he joined AT&T Bell Laboratories, Holmdel, NJ, where he has worked on the development of high-capacity analog and digitaf transmission systems. Since 1981, he has been Supervisor of the Undersea Lightwave Regenerator Group, responsible for the development of integrated electronics for fiber-optic systems. Mr. Ross is Chairman of the IEEE New Technical and Scientific Activities Committee, New York Section, and a member of the IEEE Lightwave Steering Committee.

CONCLUSION a two-chip

set including

for regeneration

all of the

of binary

electri-

signals in a 295.6-Mbit/s optical regenerator. A sophisticated 2.5-pm fully complementary bipolar integrated-circuit process was used. The special features of that process allowed us to design circuits with lhigh performance and low current drain, suitable for application in undersea repeaters. The chip set is now in production at AT&T Technologies, Reading, Pennsylvania. cal data

Stanley F. Moyer was born in Hamburg, PA, on September 8, 1931. He graduated from Capital Radio Engineering Institute, Washington, DC, in 1956. He also attended Albright College, Reading PA, and Lafeyette College, Easton, PA. In 1956, he joined Bell Laboratories and is presently located at Reading, PA. He is a Member of the Technicaf Staff, He has been engaged in the development of Complementary Bipolar Integrated Circuit (CBIC) technology since 19’70. He has been working on the development of Microwave CBIC (MCBIC) technology since 1381.

ACKNOWLEDGMENT

The authors are indebted to many colleagues who contributed to the design, development, and manufacturing process. REFERENCES

[1] P.K. Runge and P.R. Trischtta~’ The SL undersea ligh twave

system;

IEEE/OSA

J. Lightwaue Tech.ol. Dec. 1984. Ross, R.M. Paski, D.B. P.brenberg, and

D.G. G.M. Homsey, “A highly-integrated opticaf regenerator for 295.6-Mbit/s undersea optical transmission,” ZEEE/OSA J. Lighrwave Technol., Dec. 1984. [3] R.L. Rosenberg, C. Charnzas, and D.A. Fishman, “Timing recovery with SAW transversal filters in the regenerators of undersea long-haul fiber transmission systems;’ IEEE/OSA J. Lightwave Technol., Dec. 1984. [4] P.D. Davis, S.F. Moyer, and V.R. Saari, “High-slew rate monolithic

[2]

Wallace H. Eckton, Jr. (S’54-M56-SM85) was born in Brush Prairie, WA, on June 15, 1933. He received the B.S.E.E. and M. S.E.E. degrees from the University of Washington in Seattle in 1955 and 1962, respectively. He afso attended Lehigh Uniwmity in Bcthlchcm, PA. In 1960, he joined Bell Laboratories, Reading, PA, as a Member of the Technicaf Staff. From 1960 to 1971, he was engaged in the development of microwave transistors and microwave siliconintegrated circuits. He has been engaged in the development of Microwave Complementary Bipolar Integrated Circuits (MCBIC) since 1981.

336 Robert M. Pasfd (S’75-M78) received the B.S.E.E. and M. S.E.E. degrees from Purdue University, West Lafayette, IN, in 1977 and 1978, respectively. From 1977 to 1984, he was a Member of the Technicaf Staff at AT&T Bell Laboratories, Holmdel, NJ, engaged in undersea lightwave regenerator development. In 1984, he became Supervisor of the Undersea Lightwave System Integration Group, responsible for integration testine of components that will be used in the TAT-8 and TPC-3 transocemwc cable s~stems. Mr. Paski is a member of Eta Kappa Nu and Tau Beta Pi.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 2, APRIL 1986

David G. E~enberg received the B.S.E.E. and M. S.E.E. degrees from the University of Delaware, Newark, in 1978 and 1980, respectively. Since 1981, he has been a Member of the Technical Staff at AT&T Bell Laboratones, Holmdel, NJ, where he is responsible for the design of integrated circuitry for undersea fiberoptic systems.