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MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface MCP23017 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB...

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MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface

MCP23017

GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0

GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5 GPB4 GPB5 GPB6 GPB7 VDD VSS NC

1 2 3 4 5 6 7

28 27 26 25 24 23 22 21 20 19 MCP23017 18 17 16 15 8 9 10 11 121314

•1 2 3 4 5 6 7 8 9 10 11 12 13 14

GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB

28 27 26 25 24 23 22 21 20 19 18 17 16 15

GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0

GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5

GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO

MCP23S17

PDIP, SOIC, SSOP

MCP23S17

28-pin PDIP (300 mil) 28-pin SOIC (300 mil) 28-pin SSOP 28-pin QFN

28 27 26 25 24 23 22 21 20 19 18 17 16 15

QFN

Packages • • • •

•1 2 3 4 5 6 7 8 9 10 11 12 13 14

GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS NC SCL SDA NC

PDIP, SOIC, SSOP

SCL SDA NC A0 A1 A2 RESET

• 16-bit remote bidirectional I/O port - I/O pins default to input • High-speed I2C™ interface (MCP23017) - 100 kHz - 400 kHz - 1.7 MHz • High-speed SPI interface (MCP23S17) - 10 MHz (max.) • Three hardware address pins to allow up to eight devices on the bus • Configurable interrupt output pins - Configurable as active-high, active-low or open-drain • INTA and INTB can be configured to operate independently or together • Configurable interrupt source - Interrupt-on-change from configured register defaults or pin changes • Polarity Inversion register to configure the polarity of the input port data • External Reset input • Low standby current: 1 µA (max.) • Operating voltage: - 1.8V to 5.5V @ -40°C to +85°C - 2.7V to 5.5V @ -40°C to +85°C - 4.5V to 5.5V @ -40°C to +125°C

Package Types

MCP23017

Features

QFN GPB4 GPB5 GPB6 GPB7 VDD VSS

28 27 26 25 24 23 22 21 20 19 MCP23S17 18 17 16 15 8 9 10 11 121314

GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB

SCK SI SO A0 A1 A2 RESET

CS

1 2 3 4 5 6 7

© 2007 Microchip Technology Inc.

DS21952B-page 1

MCP23017/MCP23S17 Functional Block Diagram MCP23S17

CS SCK SI SO

SPI

MCP23017 SCL SDA

I2C™ 3

A2:A0

Decode

RESET INTA INTB

GPIO

GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0

GPIO

GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0

Serializer/ Deserializer

Control 16

Interrupt Logic 8

Configuration/ Control Registers

DS21952B-page 2

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.0

DEVICE OVERVIEW

The MCP23017/MCP23S17 (MCP23X17) device family provides 16-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface. • MCP23017 – I2C interface • MCP23S17 – SPI interface The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B). The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The 16-bit I/O port functionally consists of two 8-bit ports (PORTA and PORTB). The MCP23X17 can be configured to operate in the 8-bit or 16-bit modes via IOCON.BANK.

© 2007 Microchip Technology Inc.

There are two interrupt pins, INTA and INTB, that can be associated with their respective ports, or can be logically OR’ed together so that both pins will activate if either port causes an interrupt. The interrupt output can be configured to activate under two conditions (mutually exclusive): 1.

2.

When any input state differs from its corresponding Input Port register state. This is used to indicate to the system master that an input state has changed. When an input state differs from a preconfigured register value (DEFVAL register).

The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pins are used to determine the device address.

DS21952B-page 3

MCP23017/MCP23S17 1.1

Pin Descriptions

TABLE 1-1:

PINOUT DESCRIPTION PDIP/ SOIC/ SSOP

QFN

Pin Type

GPB0

1

25

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB1

2

26

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB2

3

27

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB3

4

28

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB4

5

1

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB5

6

2

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB6

7

3

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPB7

8

4

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

VDD

9

5

P

Power

VSS

10

6

P

Ground

Pin Name

Function

NC/CS

11

7

I

NC (MCP23017), Chip Select (MCP23S17)

SCL/SCK

12

8

I

Serial clock input

SDA/SI

13

9

I/O

Serial data I/O (MCP23017), Serial data input (MCP23S17)

NC/SO

14

10

O

NC (MCP23017), Serial data out (MCP23S17)

A0

15

11

I

Hardware address pin. Must be externally biased.

A1

16

12

I

Hardware address pin. Must be externally biased.

A2

17

13

I

Hardware address pin. Must be externally biased.

RESET

18

14

I

Hardware reset. Must be externally biased.

INTB

19

15

O

Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.

INTA

20

16

O

Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.

GPA0

21

17

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA1

22

18

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA2

23

19

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA3

24

20

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA4

25

21

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA5

26

22

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA6

27

23

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

GPA7

28

24

I/O

Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

DS21952B-page 4

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.2

Power-on Reset (POR)

1.3.1

The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in Section 2.0 “Electrical Characteristics”. When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation.

1.3

Serial Interface

This block handles the functionality of the I2C (MCP23017) or SPI (MCP23S17) interface protocol. The MCP23X17 contains 22 individual registers (11 register pairs) that can be addressed through the Serial Interface block, as shown in Table 1-2.

TABLE 1-2:

REGISTER ADDRESSES

Address Address IOCON.BANK = 1 IOCON.BANK = 0 00h 10h 01h 11h 02h 12h 03h 13h 04h 14h 05h 15h 06h 16h 07h 17h 08h 18h 09h 19h 0Ah 1Ah

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h

Access to: IODIRA IODIRB IPOLA IPOLB GPINTENA GPINTENB DEFVALA DEFVALB INTCONA INTCONB IOCON IOCON GPPUA GPPUB INTFA INTFB INTCAPA INTCAPB GPIOA GPIOB OLATA OLATB

BYTE MODE AND SEQUENTIAL MODE

The MCP23X17 family has the ability to operate in Byte mode or Sequential mode (IOCON.SEQOP). Byte Mode disables automatic Address Pointer incrementing. When operating in Byte mode, the MCP23X17 family does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches. A special mode (Byte mode with IOCON.BANK = 0) causes the address pointer to toggle between associated A/B register pairs. For example, if the BANK bit is cleared and the Address Pointer is initially set to address 12h (GPIOA) or 13h (GPIOB), the pointer will toggle between GPIOA and GPIOB. Note that the Address Pointer can initially point to either address in the register pair. Sequential mode enables automatic address pointer incrementing. When operating in Sequential mode, the MCP23X17 family increments its address counter after each byte during the data transfer. The Address Pointer automatically rolls over to address 00h after accessing the last register. These two modes are not to be confused with single writes/reads and continuous writes/reads that are serial protocol sequences. For example, the device may be configured for Byte mode and the master may perform a continuous read. In this case, the MCP23X17 would not increment the Address Pointer and would repeatedly drive data from the same location.

1.3.2 1.3.2.1

I2C INTERFACE I2C Write Operation

The I2C write operation includes the control byte and register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23017. The operation is ended with a Stop (P) or Restart (SR) condition being generated by the master. Data is written to the MCP23017 after every byte transfer. If a Stop or Restart condition is generated during a data transfer, the data will not be written to the MCP23017. Both “byte writes” and “sequential writes” are supported by the MCP23017. If Sequential mode is enabled (IOCON, SEQOP = 0) (default), the MCP23017 increments its address counter after each ACK during the data transfer.

© 2007 Microchip Technology Inc.

DS21952B-page 5

MCP23017/MCP23S17 1.3.2.2

I2C Read Operation

2

I C Read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = 1). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition.

1.3.2.3

I2C Sequential Write/Read

For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see Section 1.3.1 “Byte Mode and Sequential Mode” for details regarding sequential operation control). The sequence ends with the master sending a Stop or Restart condition. The MCP23017 Address Pointer will roll over to address zero after reaching the last register address. Refer to Figure 1-1.

1.3.3 1.3.3.1

SPI INTERFACE SPI Write Operation

The SPI write operation is started by lowering CS. The Write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte.

1.3.3.2

SPI Read Operation

The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device.

1.3.3.3

SPI Sequential Write/Read

For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the Address Pointer. (see Section 1.3.1 “Byte Mode and Sequential Mode” for details regarding sequential operation control). The sequence ends by the raising of CS. The MCP23S17 Address Pointer will roll over to address zero after reaching the last register address.

DS21952B-page 6

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 MCP23017 I2C™ DEVICE PROTOCOL

FIGURE 1-1: S - Start SR - Restart

S

OP

DIN

W ADDR

DIN

....

P

P - Stop w

- Write

SR

OP

R

DOUT ....

DOUT

P

SR

OP

W

DIN

DIN

P

R - Read OP

- Device opcode

ADDR

- Device register address

DOUT

- Data out from MCP23017

DIN

....

P

- Data in to MCP23017

OP

S

DOUT

R

SR

SR

OP

W

OP

DOUT

....

R

ADDR

P

DOUT

....

DOUT

P

DIN

....

DIN

P

P

Byte and Sequential Write Byte

S

OP

W

ADDR

DIN

Sequential

S

OP

W ADDR

DIN

P DIN

....

P

Byte and Sequential Read Byte S

OP

W

SR

OP

R

DOUT

Sequential S

OP

W

SR

OP

R

DOUT

© 2007 Microchip Technology Inc.

P ....

DOUT

P

DS21952B-page 7

MCP23017/MCP23S17 1.4

Hardware Address Decoder

The hardware address pins are used to determine the device address. To address a device, the corresponding address bits in the control byte must match the pin state. The pins must be biased externally.

Control Byte S

ADDRESSING I2C DEVICES (MCP23017)

1.4.1

0

0

A2 A1 A0 R/W ACK

R/W bit ACK bit R/W = 0 = write R/W = 1 = read

FIGURE 1-3:

SPI CONTROL BYTE FORMAT

CS

The MCP23S17 is a slave SPI device. The slave address contains four fixed bits and three user-defined hardware address bits (if enabled via IOCON.HAEN) (pins A2, A1 and A0) with the read/write bit filling out the control byte. Figure 1-3 shows the control byte format. The address pins should be externally biased even if disabled (IOCON.HAEN = 0).

Control Byte 0

1

0

0

A2 A1 A0 R/W

Slave Address R/W bit R/W = 0 = write R/W = 1 = read

I2C™ ADDRESSING REGISTERS

FIGURE 1-4: 0

0

Start bit

ADDRESSING SPI DEVICES (MCP23S17)

S

1

Slave Address

The MCP23017 is a slave I2C interface device that supports 7-bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (pins A2, A1 and A0). Figure 1-2 shows the control byte format.

1.4.2

I2C™ CONTROL BYTE FORMAT

FIGURE 1-2:

1

0

0

A2 A1 A0

0

ACK*

A7

A6

A5

A4

A3

A2

A1

A0

ACK*

R/W = 0 Device Opcode

Register Address

*The ACKs are provided by the MCP23017.

FIGURE 1-5:

SPI ADDRESSING REGISTERS

CS 0

1

0

0

A2 A1 A0 R/W * * *

A7

Device Opcode

A6

A5

A4

A3

A2

A1

A0

Register Address

* Address pins are enabled/disabled via IOCON.HAEN.

DS21952B-page 8

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.5

GPIO Port

Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port.

The GPIO module is a general purpose, 16-bit wide, bidirectional port that is functionally split into two 8-bit wide ports.

Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high-impedance.

The GPIO module contains the data ports (GPIOn), internal pull-up resistors and the output latches (OLATn).

TABLE 1-3: Register Name IODIRA

SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1) Address (hex)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

POR/RST value

00

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLA

01

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENA

02

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

GPPUA

06

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

GPIOA

09

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATA

0A

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

IODIRB

10

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLB

11

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENB

12

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

GPPUB

16

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

GPIOB

19

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATB

1A

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

TABLE 1-4:

SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0) Address (hex)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

POR/RST value

IODIRA

00

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IODIRB

01

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLA

02

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

IPOLB

03

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENA

04

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

GPINTENB

05

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

GPPUA

0C

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

GPPUB

0D

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

GPIOA

12

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

GPIOB

13

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATA

14

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

OLATB

15

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

Register Name

© 2007 Microchip Technology Inc.

DS21952B-page 9

MCP23017/MCP23S17 1.6

Configuration and Control Registers

are associated with PortB. One register (IOCON) is shared between the two ports. The PortA registers are identical to the PortB registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the “A” or “B” designator assigned) in the register tables.

There are 21 registers associated with the MCP23X17, as shown in Table 1-5 and Table 1-6. The two tables show the register mapping with the two BANK bit values. Ten registers are associated with PortA and ten

TABLE 1-5: Register Name IODIRA

CONTROL REGISTER SUMMARY (IOCON.BANK = 1) Address (hex)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

POR/RST value

00

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLA

01

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENA

02

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

DEFVALA

03

DEF7

DEF6

DEF5

DEF4

DEF3

DEF2

DEF1

DEF0

0000 0000

INTCONA

04

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

0000 0000

IOCON

05

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL



0000 0000

GPPUA

06

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

INTFA

07

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INTO

0000 0000

INTCAPA

08

ICP7

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

0000 0000

GPIOA

09

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATA

0A

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

IODIRB

10

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLB

11

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENB

12

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

DEFVALB

13

DEF7

DEF6

DEF5

DEF4

DEF3

DEF2

DEF1

DEF0

0000 0000

INTCONB

14

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

0000 0000

IOCON

15

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL



0000 0000

GPPUB

16

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

INTFB

17

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INTO

0000 0000

INTCAPB

18

ICP7

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

0000 0000

GPIOB

19

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATB

1A

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

DS21952B-page 10

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 TABLE 1-6:

CONTROL REGISTER SUMMARY (IOCON.BANK = 0) Address (hex)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

POR/RST value

IODIRA

00

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IODIRB

01

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

1111 1111

IPOLA

02

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

IPOLB

03

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

0000 0000

GPINTENA

04

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

GPINTENB

05

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

0000 0000

DEFVALA

06

DEF7

DEF6

DEF5

DEF4

DEF3

DEF2

DEF1

DEF0

0000 0000

DEFVALB

07

DEF7

DEF6

DEF5

DEF4

DEF3

DEF2

DEF1

DEF0

0000 0000

INTCONA

08

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

0000 0000

Register Name

INTCONB

09

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

0000 0000

IOCON

0A

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL



0000 0000

IOCON

0B

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL



0000 0000

GPPUA

0C

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

GPPUB

0D

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

0000 0000

INTFA

0E

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INTO

0000 0000

INTFB

0F

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INTO

0000 0000

INTCAPA

10

ICP7

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

0000 0000

INTCAPB

11

ICP7

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

0000 0000

GPIOA

12

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

GPIOB

13

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0000 0000

OLATA

14

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

OLATB

15

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

0000 0000

© 2007 Microchip Technology Inc.

DS21952B-page 11

MCP23017/MCP23S17 1.6.1

I/O DIRECTION REGISTER

Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output.

REGISTER 1-1:

IODIR – I/O DIRECTION REGISTER (ADDR 0x00)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

IO7:IO0: These bits control the direction of data I/O 1 = Pin is configured as an input. 0 = Pin is configured as an output.

DS21952B-page 12

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.2

INPUT POLARITY REGISTER

This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin.

REGISTER 1-2:

IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

IP7:IP0: These bits control the polarity inversion of the input pins 1 = GPIO register bit will reflect the opposite logic state of the input pin. 0 = GPIO register bit will reflect the same logic state of the input pin.

© 2007 Microchip Technology Inc.

DS21952B-page 13

MCP23017/MCP23S17 1.6.3

INTERRUPT-ON-CHANGE CONTROL REGISTER

The GPINTEN register controls the interrupt-onchange feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.

REGISTER 1-3:

GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

GPINT7

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

GPINT7:GPINT0: General purpose I/O interrupt-on-change bits 1 = Enable GPIO input pin for interrupt-on-change event. 0 = Disable GPIO input pin for interrupt-on-change event. Refer to INTCON and GPINTEN.

DS21952B-page 14

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.4

DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur.

REGISTER 1-4:

DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

DEF7

DEF6

DEF5

DEF4

DEF3

DEF2

DEF1

DEF0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from defaults . Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN.

© 2007 Microchip Technology Inc.

DS21952B-page 15

MCP23017/MCP23S17 1.6.5

INTERRUPT CONTROL REGISTER

The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.

REGISTER 1-5:

INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-change 1 = Controls how the associated pin value is compared for interrupt-on-change. 0 = Pin value is compared against the previous pin value. Refer to INTCON and GPINTEN.

DS21952B-page 16

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.6

CONFIGURATION REGISTER

The IOCON register configuring the device:

contains

several

bits

for

The BANK bit changes how the registers are mapped (see Table 1-5 and Table 1-6 for more details). • If BANK = 1, the registers associated with each port are segregated. Registers associated with PORTA are mapped from address 00h - 0Ah and registers associated with PORTB are mapped from 10h - 1Ah. • If BANK = 0, the A/B registers are paired. For example, IODIRA is mapped to address 00h and IODIRB is mapped to the next address (address 01h). The mapping for all registers is from 00h 15h. It is important to take care when changing the BANK bit as the address mapping changes after the byte is clocked into the device. The address pointer may point to an invalid location after the bit is modified. For example, if the device is configured to automatically increment its internal Address Pointer, the following scenario would occur: • BANK = 0 • Write 80h to address 0Ah (IOCON) to set the BANK bit • Once the write completes, the internal address now points to 0Bh which is an invalid address when the BANK bit is set. For this reason, it is advised to only perform byte writes to this register when changing the BANK bit.

© 2007 Microchip Technology Inc.

The MIRROR bit controls how the INTA and INTB pins function with respect to each other. • When MIRROR = 1, the INTn pins are functionally OR’ed so that an interrupt on either port will cause both pins to activate. • When MIRROR = 0, the INT pins are separated. Interrupt conditions on a port will cause its respective INT pin to activate. The Sequential Operation (SEQOP) controls the incrementing function of the Address Pointer. If the address pointer is disabled, the Address Pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register. The Slew Rate (DISSLW) bit controls the slew rate function on the SDA pin. If enabled, the SDA slew rate will be controlled when driving from a high to low. The Hardware Address Enable (HAEN) bit enables/ disables hardware addressing on the MCP23S17 only. The address pins (A2, A1 and A0) must be externally biased, regardless of the HAEN bit value. If enabled (HAEN = 1), the device’s hardware address matches the address pins. If disabled (HAEN = 0), the device’s hardware address is A2 = A1 = A0 = 0. The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration. Erasing this bit overrides the INTPOL bit. The Interrupt Polarity (INTPOL) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull.

DS21952B-page 17

MCP23017/MCP23S17 REGISTER 1-6:

IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

U-0

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL



bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

BANK: Controls how the registers are addressed 1 = The registers associated with each port are separated into different banks 0 = The registers are in the same bank (addresses are sequential)

bit 6

MIRROR: INT Pins Mirror bit 1 = The INT pins are internally connected 0 = The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB

bit 5

SEQOP: Sequential Operation mode bit. 1 = Sequential operation disabled, address pointer does not increment. 0 = Sequential operation enabled, address pointer increments.

bit 4

DISSLW: Slew Rate control bit for SDA output. 1 = Slew rate disabled. 0 = Slew rate enabled.

bit 3

HAEN: Hardware Address Enable bit (MCP23S17 only). Address pins are always enabled on MCP23017. 1 = Enables the MCP23S17 address pins. 0 = Disables the MCP23S17 address pins.

bit 2

ODR: This bit configures the INT pin as an open-drain output. 1 = Open-drain output (overrides the INTPOL bit). 0 = Active driver output (INTPOL bit sets the polarity).

bit 1

INTPOL: This bit sets the polarity of the INT output pin. 1 = Active-high. 0 = Active-low.

bit 0

Unimplemented: Read as ‘0’.

DS21952B-page 18

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.7

PULL-UP RESISTOR CONFIGURATION REGISTER

The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 kΩ resistor.

REGISTER 1-7:

GPPU – GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input) . 1 = Pull-up enabled. 0 = Pull-up disabled.

© 2007 Microchip Technology Inc.

DS21952B-page 19

MCP23017/MCP23S17 1.6.8

INTERRUPT FLAG REGISTER

The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. This register is ‘read-only’. Writes to this register will be ignored.

REGISTER 1-8:

INTF – INTERRUPT FLAG REGISTER (ADDR 0x07)

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) . 1 = Pin caused interrupt. 0 = Interrupt not pending.

DS21952B-page 20

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.9

INTERRUPT CAPTURE REGISTER

The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO.

REGISTER 1-9:

INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)

R-x

R-x

R-x

R-x

R-x

R-x

R-x

R-x

ICP7

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change 1 = Logic-high. 0 = Logic-low.

© 2007 Microchip Technology Inc.

DS21952B-page 21

MCP23017/MCP23S17 1.6.10

PORT REGISTER

The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register.

REGISTER 1-10:

GPIO – GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

GP7:GP0: These bits reflect the logic level on the pins 1 = Logic-high. 0 = Logic-low.

DS21952B-page 22

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.6.11

OUTPUT LATCH REGISTER (OLAT)

The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.

REGISTER 1-11:

OLAT – OUTPUT LATCH REGISTER 0 (ADDR 0x0A)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

x = Bit is unknown

OL7:OL0: These bits reflect the logic level on the output latch 1 = Logic-high. 0 = Logic-low.

© 2007 Microchip Technology Inc.

DS21952B-page 23

MCP23017/MCP23S17 1.7

Interrupt Logic

1.7.2

If enabled, the MCP23X17 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. Each pin is individually configurable as follows: • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt-on-Change (IOC). The interrupt control module uses the following registers/bits: • IOCON.MIRROR – controls if the two interrupt pins mirror each other • GPINTEN – Interrupt enable register • INTCON – Controls the source for the IOC • DEFVAL – Contains the register default for IOC operation

1.7.1

INTA AND INTB

There are two interrupt pins: INTA and INTB. By default, INTA is associated with GPAn pins (PortA) and INTB is associated with GPBn pins (PortB). Each port has an independent signal which is cleared if its associated GPIO or INTCAP register is read.

1.7.1.1

Mirroring the INT pins

Additionally, the INTn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. This is controlled via IOCON.MIRROR. If IOCON.MIRROR = 0, the internal signals are routed independently to the INTA and INTB pads. If IOCON.MIRROR = 1, the internal signals are OR’ed together and routed to the INTn pads. In this case, the interrupt will only be cleared if the associated GPIO or INTCAP is read (see Table 1-7).

TABLE 1-7: Interrupt Condition GPIOA GPIOB

GPIOA and GPIOB

INTERRUPT OPERATION (IOCON.MIRROR = 1) Read Portn *

IOC FROM PIN CHANGE

If enabled, the MCP23X17 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC enabled pins will be compared. Refer to Register 1-3 and Register 1-5.

1.7.3

IOC FROM REGISTER DEFAULT

If enabled, the MCP23X17 will generate an interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC enabled pins will be compared. Refer to Register 1-3, Register 1-5 and Register 1-4.

1.7.4

INTERRUPT OPERATION

The INTn interrupt output can be configured as activelow, active-high or open-drain via the IOCON register. Only those pins that are configured as an input (IODIR register) with Interrupt-On-Change (IOC) enabled (IOINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin. Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP. The interrupt will remain active until the INTCAP or GPIO register is read. Writing to these registers will not affect the interrupt. The interrupt condition will be cleared after the LSb of the data is clocked out during a read command of GPIO or INTCAP. The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO. Note:

The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update.

Interupt Result

PortA

Clear

PortB

Unchanged

PortA

Unchanged

PortB

Clear

PortA

Unchanged

PortB

Unchanged

Both PortA and PortB

Clear

* Port n = GPIOn or INTCAPn

DS21952B-page 24

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 1.7.5

INTERRUPT CONDITIONS

FIGURE 1-7:

INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT

There are two possible configurations that cause interrupts (configured via INTCON): 1.

2.

Pins configured for interrupt-on-pin change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e., after reading GPIO or INTCAP). For example, an interrupt occurs by an input changing from ‘1’ to ‘0’. The new initial state for the pin is a logic 0 after the interrupt is cleared. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTCAP or GPIO is read.

See Figure 1-6 and Figure 1-7 for more information on interrupt operations.

FIGURE 1-6:

INTERRUPT-ON-PIN CHANGE

DEFVAL REGISTER GP:

7

6

5

4

3

2

1

0

X

X

X

X

X

0

X

X

GP2 Pin

INT Pin

ACTIVE

Port value is captured into INTCAP

ACTIVE

Read GPIU or INTCAP (INT clears only if interrupt condition does not exist.)

GPx

INT Port value is captured into INTCAP

ACTIVE Read GPIO or INTCAP

© 2007 Microchip Technology Inc.

ACTIVE Port value is captured into INTCAP

DS21952B-page 25

MCP23017/MCP23S17 NOTES:

DS21952B-page 26

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 2.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................. -40°C to +125°C Storage temperature ............................................................................................................................... -65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V) Total power dissipation (Note) .............................................................................................................................700 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................125 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA Maximum output current sunk by any output pin ....................................................................................................25 mA Maximum output current sourced by any output pin ...............................................................................................25 mA Note:

Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOL x IOL)



NOTE: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

© 2007 Microchip Technology Inc.

DS21952B-page 27

MCP23017/MCP23S17 2.1

DC Characteristics

DC Characteristics Param No.

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

Characteristic

Sym

Min

Typ (Note 1(

Max

Units

Conditions

D001

Supply Voltage

VDD

1.8



5.5

V

D002

VDD Start Voltage to Ensure Power-on Reset

VPOR



VSS



V

D003

VDD Rise Rate to Ensure Power-on Reset

SVDD

0.05





V/ms

D004

Supply Current

IDD





1

mA

D005

Standby current

IDDS





1

µA





3

µA

VSS



0.15 VDD

V

VSS



0.2 VDD

V

0.25 VDD + 0.8



VDD

V

0.8 VDD



VDD

V

For entire VDD range

IIL





±1

µA

VSS ≤ VPIN ≤ VDD

Design guidance only. Not tested. SCL/SCK = 1 MHz 4.5V-5.5V @ +125°C (Note 1)

Input Low Voltage D030

A0, A1 (TTL buffer)

D031

CS, GPIO, SCL/SCK, SDA, A2, RESET (Schmitt Trigger)

VIL

Input High Voltage D040

A0, A1 (TTL buffer)

D041

CS, GPIO, SCL/SCK, SDA, A2, RESET (Schmitt Trigger)

VIH

Input Leakage Current D060

I/O port pins Output Leakage Current

D065

I/O port pins

ILO





±1

µA

VSS ≤ VPIN ≤ VDD

D070

GPIO weak pull-up current

IPU

40

75

115

µA

VDD = 5V, GP Pins = VSS –40°C ≤ TA ≤ +85°C

VOL





0.6

V

IOL = 8.0 mA, VDD = 4.5V





0.6

V

IOL = 1.6 mA, VDD = 4.5V

Output Low-Voltage D080

GPIO INT SO, SDA





0.6

V

IOL = 3.0 mA, VDD = 1.8V

SDA





0.8

V

IOL = 3.0 mA, VDD = 4.5V

VDD – 0.7





V

IOH = -3.0 mA, VDD = 4.5V

VDD – 0.7





Output High-Voltage D090

GPIO, INT, SO

VOH

IOH = -400 µA, VDD = 1.8V

Capacitive Loading Specs on Output Pins D101

GPIO, SO, INT

CIO





50

pF

D102

SDA

CB





400

pF

Note 1:

This parameter is characterized, not 100% tested.

DS21952B-page 28

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 FIGURE 2-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin

1 kΩ SCL and SDA pin MCP23017

50 pF 135 pF

FIGURE 2-2:

RESET AND DEVICE RESET TIMER TIMING

VDD RESET 30

32

Internal RESET

34 Output pin

© 2007 Microchip Technology Inc.

DS21952B-page 29

MCP23017/MCP23S17 TABLE 2-1:

DEVICE RESET SPECIFICATIONS Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

AC Characteristics Param No.

Characteristic

Sym

Min

Typ(1)

Max

Units

30

RESET Pulse Width (Low)

TRSTL

1





µs

32

Device Active After Reset high

THLD



0



ns

34

Output High-Impedance From RESET Low

TIOZ





1

µs

Note 1:

Conditions

VDD = 5.0V

This parameter is characterized, not 100% tested.

FIGURE 2-3:

I2C™ BUS START/STOP BITS TIMING

SCL

93

91 90

92

SDA

Stop Condition

Start Condition

FIGURE 2-4:

I2C™ BUS DATA TIMING 103

102

100 101

SCL

90

106

91

107

SDA In 109

109

92 110

SDA Out

DS21952B-page 30

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 TABLE 2-2:

I2C™ BUS DATA REQUIREMENTS

2

I C™ AC Characteristics Param No. 100

Characteristic

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF Min

Typ

100 kHz mode

4.0





µs

1.8V–5.5V (I-Temp)

400 kHz mode

0.6





µs

2.7V–5.5V (I-Temp)

0.12





µs

4.5V–5.5V (E-Temp)

4.7





µs

1.8V–5.5V (I-Temp)

400 kHz mode

1.3





µs

2.7V–5.5V (I-Temp)

1.7 MHz mode

0.32





µs

4.5V–5.5V (E-Temp)





1000

ns

1.8V–5.5V (I-Temp)

Clock High Time:

Sym

Clock Low Time:

TLOW

100 kHz mode

102

SDA and SCL Rise Time: 100 kHz mode

103

TR (Note 1)

400 kHz mode

20 + 0.1 CB(2)



300

ns

2.7V–5.5V (I-Temp)

1.7 MHz mode

20



160

ns

4.5V–5.5V (E-Temp)

SDA and SCL Fall Time: 100 kHz mode

TF (Note 1)





300

ns

1.8V–5.5V (I-Temp)

20 + 0.1 CB(2)



300

ns

2.7V–5.5V (I-Temp)

20



80

ns

4.5V–5.5V (E-Temp)

4.7





µs

1.8V–5.5V (I-Temp)

400 kHz mode

0.6





µs

2.7V–5.5V (I-Temp)

1.7 MHz mode

0.16





µs

4.5V–5.5V (E-Temp)

100 kHz mode

4.0





µs

1.8V–5.5V (I-Temp)

400 kHz mode

0.6





µs

2.7V–5.5V (I-Temp)

1.7 MHz mode

0.16





µs

4.5V–5.5V (E-Temp)

400 kHz mode 1.7 MHz mode 90

START Condition Setup Time:

TSU:STA

100 kHz mode

91

106

START Condition Hold Time:

Data Input Hold Time:

THD:STA

THD:DAT

100 kHz mode

0



3.45

µs

1.8V–5.5V (I-Temp)

400 kHz mode

0



0.9

µs

2.7V–5.5V (I-Temp)

0



0.15

µs

4.5V–5.5V (E-Temp)

250





ns

1.8V–5.5V (I-Temp)

1.7 MHz mode 107

Data Input Setup Time:

TSU:DAT

100 kHz mode

92

Note 1: 2:

Conditions

THIGH

1.7 MHz mode 101

Max Units

400 kHz mode

100





ns

2.7V–5.5V (I-Temp)

1.7 MHz mode

0.01





µs

4.5V–5.5V (E-Temp)

100 kHz mode

4.0





µs

1.8V–5.5V (I-Temp)

400 kHz mode

0.6





µs

2.7V–5.5V (I-Temp)

1.7 MHz mode

0.16





µs

4.5V–5.5V (E-Temp)

Stop Condition Setup Time:

TSU:STO

This parameter is characterized, not 100% tested. CB is specified to be from 10 to 400 pF.

© 2007 Microchip Technology Inc.

DS21952B-page 31

MCP23017/MCP23S17 I2C™ BUS DATA REQUIREMENTS (CONTINUED)

TABLE 2-2:

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF

2

I C™ AC Characteristics Param No.

Characteristic

109

Sym

Output Valid From Clock:





Max Units

Conditions

3.45

µs

1.8V–5.5V (I-Temp)

400 kHz mode





0.9

µs

2.7V–5.5V (I-Temp)

1.7 MHz mode





0.18

µs

4.5V–5.5V (E-Temp)

4.7





µs

1.8V–5.5V (I-Temp)

Bus Free Time:

TBUF

100 kHz mode 400 kHz mode

1.3





µs

2.7V–5.5V (I-Temp)

1.7 MHz mode

N/A



N/A

µs

4.5V – 5.5V (E-Temp)





400

pF

Note 1





100

pF

Note 1

Bus Capacitive Loading:

CB

100 kHz and 400 kHz 1.7 MHz Input Filter Spike Suppression (SDA and SCL)

Note 1: 2:

Typ

TAA

100 kHz mode

110

Min

TSP

100 kHz and 400 kHz





50

ns

1.7 MHz





10

ns

Spike suppression off

This parameter is characterized, not 100% tested. CB is specified to be from 10 to 400 pF.

FIGURE 2-5:

SPI INPUT TIMING 3

CS 11 Mode 1,1

6

1

7

10

2

SCK Mode 0,0 4

5

SI MSB in

SO

DS21952B-page 32

LSB in High-Impedance

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 FIGURE 2-6:

SPI OUTPUT TIMING

CS 8

SCK

2

9

Mode 1,1 Mode 0,0

12 SO

MSB out

LSB out

Don’t Care

SI

TABLE 2-3:

SPI INTERFACE AC CHARACTERISTICS

SPI Interface AC Characteristics Param No.

14

13

Characteristic Clock Frequency

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Sym

Min

Typ

Max

Units

Conditions

FCLK





5

MHz

1.8V–5.5V (I-Temp)





10

MHz

2.7V–5.5V (I-Temp) 4.5V–5.5V (E-Temp)





10

MHz

1

CS Setup Time

TCSS

50





ns

2

CS Hold Time

TCSH

100





ns

1.8V–5.5V (I-Temp)

50





ns

2.7V–5.5V (I-Temp)

3

4

5

CS Disable Time

Data Setup Time

Data Hold Time

TCSD

TSU

THD

50





ns

4.5V–5.5V (E-Temp)

100





ns

1.8V–5.5V (I-Temp)

50





ns

2.7V–5.5V (I-Temp)

50





ns

4.5V–5.5V (E-Temp)

20





ns

1.8V–5.5V (I-Temp)

10





ns

2.7V–5.5V (I-Temp)

10





ns

4.5V–5.5V (E-Temp)

20





ns

1.8V–5.5V (I-Temp)

10





ns

2.7V–5.5V (I-Temp)

10





ns

4.5V–5.5V (E-Temp)

6

CLK Rise Time

TR





2

µs

Note 1

7

CLK Fall Time

TF





2

µs

Note 1

8

Clock High Time

THI

90





ns

1.8V–5.5V (I-Temp)

45





ns

2.7V–5.5V (I-Temp)

45





ns

4.5V–5.5V (E-Temp)

Note 1:

This parameter is characterized, not 100% tested.

© 2007 Microchip Technology Inc.

DS21952B-page 33

MCP23017/MCP23S17 TABLE 2-3:

SPI INTERFACE AC CHARACTERISTICS (CONTINUED)

SPI Interface AC Characteristics Param No. 9

Characteristic Clock Low Time

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Sym

Min

Typ

Max

Units

TLO

90





ns

Conditions 1.8V–5.5V (I-Temp)

45





ns

2.7V–5.5V (I-Temp)

45





ns

4.5V–5.5V (E-Temp)

10

Clock Delay Time

TCLD

50





ns

11

Clock Enable Time

TCLE

50





ns

12

Output Valid from Clock Low

TV





90

ns

1.8V–5.5V (I-Temp)





45

ns

2.7V–5.5V (I-Temp)





45

ns

4.5V–5.5V (E-Temp)

13

Output Hold Time

THO

0





ns

14

Output Disable Time

TDIS





100

ns

Note 1:

This parameter is characterized, not 100% tested.

FIGURE 2-7:

GPIO AND INT TIMING

SCL/SCK SDA/SI In

D1

D0 LSb of data byte zero during a write or read command, depending on parameter

50

GPn Output Pin 51 INT Pin

GPn Input Pin

INT Pin Active

Inactive 53

52 Register Loaded

DS21952B-page 34

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 TABLE 2-4:

GP AND INT PINS

AC Characteristics

Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

Param No.

Characteristic

Sym

Min

Typ

Max

Units

50

Serial Data to Output Valid

TGPOV





500

ns

51

Interrupt Pin Disable Time

TINTD





600

ns

52

GP Input Change to Register Valid

TGPIV





450

ns

53

IOC Event to INT Active

TGPINT





600

ns

Glitch Filter on GP Pins

TGLITCH





150

ns

Note 1:

Conditions

Note 1

This parameter is characterized, not 100% tested

© 2007 Microchip Technology Inc.

DS21952B-page 35

MCP23017/MCP23S17 NOTES:

DS21952B-page 36

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 3.0

PACKAGING INFORMATION

3.1

Package Marking Information 28-Lead PDIP (Skinny DIP)

Example:

XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNN

28-Lead QFN

e3 MCP23017-E/SP^^ 0648256

Example:

XXXXXXXX XXXXXXXX YYWWNNN

23017 e3 E/ML^^ 0648256

28-Lead SOIC

Example:

XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX

e3 MCP23017-E/SO^^

0648256

YYWWNNN

Example:

28-Lead SSOP

XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN

Legend: XX...X Y YY WW NNN

e3

* Note:

MCP23017 e3 E/SS^^ 0648256

Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.

In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

© 2007 Microchip Technology Inc.

DS21952B-page 37

MCP23017/MCP23S17 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

N NOTE 1 E1

1

2

3 D E A2

A

L

c

b1

A1

b

e

eB

Units Dimension Limits Number of Pins

INCHES MIN

N

NOM

MAX

28

Pitch

e

Top to Seating Plane

A





.200

Molded Package Thickness

A2

.120

.135

.150

Base to Seating Plane

A1

.015





Shoulder to Shoulder Width

E

.290

.310

.335

Molded Package Width

E1

.240

.285

.295

Overall Length

D

1.345

1.365

1.400

Tip to Seating Plane

L

.110

.130

.150

Lead Thickness

c

.008

.010

.015

b1

.040

.050

.070

b

.014

.018

.022

eB





Upper Lead Width Lower Lead Width Overall Row Spacing §

.100 BSC

.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B

DS21952B-page 38

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D

D2

EXPOSED PAD

e E

b

E2 2

2

1

1

N

K N

NOTE 1

L BOTTOM VIEW

TOP VIEW

A

A3

A1 Units Dimension Limits Number of Pins

MILLIMETERS MIN

N

NOM

MAX

28

Pitch

e

Overall Height

A

0.80

0.65 BSC 0.90

1.00

Standoff

A1

0.00

0.02

0.05

Contact Thickness

A3

0.20 REF

Overall Width

E

Exposed Pad Width

E2

Overall Length

D

Exposed Pad Length

D2

3.65

3.70

4.20

b

0.23

0.30

0.35

Contact Length

L

0.50

0.55

0.70

Contact-to-Exposed Pad

K

0.20





Contact Width

6.00 BSC 3.65

3.70

4.20

6.00 BSC

Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B

© 2007 Microchip Technology Inc.

DS21952B-page 39

MCP23017/MCP23S17 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N

E E1 NOTE 1 1 2 3 b

e

h

α

A2

A

h c

φ

L A1

Units Dimension Limits Number of Pins

β

L1

MILLMETERS MIN

N

NOM

MAX

28

Pitch

e

Overall Height

A



1.27 BSC –

Molded Package Thickness

A2

2.05





Standoff §

A1

0.10



0.30

Overall Width

E

Molded Package Width

E1

7.50 BSC

Overall Length

D

17.90 BSC

2.65

10.30 BSC

Chamfer (optional)

h

0.25



0.75

Foot Length

L

0.40



1.27

Footprint

L1

1.40 REF

Foot Angle Top

φ







Lead Thickness

c

0.18



0.33

Lead Width

b

0.31



0.51

Mold Draft Angle Top

α





15°

Mold Draft Angle Bottom

β





15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B

DS21952B-page 40

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N

E E1

1 2 NOTE 1

b e

c A2

A

φ

A1

L

L1 Units Dimension Limits Number of Pins

MILLIMETERS MIN

N

NOM

MAX

28

Pitch

e

Overall Height

A



0.65 BSC –

2.00

Molded Package Thickness

A2

1.65

1.75

1.85

Standoff

A1

0.05





Overall Width

E

7.40

7.80

8.20

Molded Package Width

E1

5.00

5.30

5.60

Overall Length

D

9.90

10.20

10.50

Foot Length

L

0.55

0.75

0.95

Footprint

L1

1.25 REF

Lead Thickness

c

0.09



Foot Angle

φ





0.25 8°

Lead Width

b

0.22



0.38

Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B

© 2007 Microchip Technology Inc.

DS21952B-page 41

MCP23017/MCP23S17 NOTES:

DS21952B-page 42

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 APPENDIX A:

REVISION HISTORY

Revision B (February 2007) 1. 2. 3. 4.

Changed Byte and Sequential Read in Figure 1-1 from “R” to “W”. Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. Added disclaimers to package outline drawings. Updated package outline drawings.

Revision A (June 2005) • Original Release of this Document.

© 2007 Microchip Technology Inc.

DS21952B-page 39

MCP23017/MCP23S17 NOTES:

DS21952B-page 40

© 2007 Microchip Technology Inc.

MCP23017/MCP23S17 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device

Device

X

/XX

Temperature Range

Package



Package

a) b)

MCP23017: MCP23017T: MCP23S17: MCP23S17T:

Temperature Range

Examples:

16-Bit I/O Expander w/I2C™ Interface 16-Bit I/O Expander w/I2C Interface (Tape and Reel) 16-Bit I/O Expander w/SPI Interface 16-Bit I/O Expander w/SPI Interface (Tape and Reel)

E

=

-40°C to +125°C (Extended)

ML SP SO SS

= = = =

Plastic Quad, Flat No Leads (QFN), 28-lead Plastic DIP (300 mil Body), 28-Lead Plastic SOIC (300 mil Body), 28-Lead SSOP, (209 mil Body, 5.30 mm), 28-Lead

c)

d) e)

a) b) c)

d) e)

© 2007 Microchip Technology Inc.

MCP23017-E/SP:

Extended Temp., 28LD PDIP package. MCP23017-E/SO: Extended Temp., 28LD SOIC package. MCP23017T-E/SO: Tape and Reel, Extended Temp., 28LD SOIC package. MCP23017-E/SS: Extended Temp., 28LD SSOP package. MCP23017T-E/SS: Tape and Reel, Extended Temp., 28LD SSOP package. MCP23S17-E/SP:

Extended Temp., 28LD PDIP package. MCP23S17-E/SO: Extended Temp., 28LD SOIC package. MCP23S17T-E/SO: Tape and Reel, Extended Temp., 28LD SOIC package. MCP23S17-E/SS: Extended Temp., 28LD SSOP package. MCP23S17T-E/SS: Tape and Reel, Extended Temp., 28LD SSOP package.

DS21952B-page 41

MCP23017/MCP23S17 NOTES:

DS21952B-page 42

© 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: •

Microchip products meet the specification contained in their particular Microchip Data Sheet.



Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.



There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.



Microchip is willing to work with the customer who is concerned about the integrity of their code.



Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

© 2007 Microchip Technology Inc.

DS21952B-page 43

WORLDWIDE SALES AND SERVICE AMERICAS

ASIA/PACIFIC

ASIA/PACIFIC

EUROPE

Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com

Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431

India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632

Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829

India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513

France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44

Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509

Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889

Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302

China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521

Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934

China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431

Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086

China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205

Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069

China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066

Singapore Tel: 65-6334-8870 Fax: 65-6334-8850

China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393

Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459

China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760

Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803

China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571

Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102

China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118

Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820

China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256

12/08/06

DS21952B-page 44

© 2007 Microchip Technology Inc.