STEVE EDN080306DI4217 FIGURE 1
CURRENT SOURCE 5V
5
5V 5V
3
C3 100 nF
8 IC2A TS3702 2 � 4 3
DC-CONTROL VOLTAGE 0 TO 2.56V
R6 100 C4 1 nF
�
NOTES: IC1 POWERED AT 5V. CONNECT A 100-nF DECOUPLING CAPACITOR CLOSE TO IC1’s POWER-SUPPLY PINS.
TRIGGER INPUT 5V 0V
6 S
Q
1
CLK IC1A CD4013B 2 Q R 4 C2 R4 100 pF 10k
1
DELAYED PULSE_OUT
D
8 S
IC1B CD4013B 11 CLK R 10
Q
Q
IO 100 �A
Q3 2N2222A
VREF 1.233V IC3 LM4041
Q1 2N5087
R5 13 100k
12
R1 1.33k 0.1% R2 11k 0.1%
DELAYED PULSE_OUT
D1 1N4148
9 OPTIONAL
D
C1 10 nF 1%
Q2 2N5087
R3 18k
NC RAMP VOLTAGE
Figure 1 The rising edge of a trigger input starts a precision ramp voltage that compares with a control voltage, generating a precise delay.
